Various comparator logic circuits have been developed that can be used to compare two analog input signals and providing a digital output signal indicating which of the two input signals is larger. Comparators are non-linear circuits commonly used to digitize analog signals. The comparator may be combined with a latch, in order to store the value of the digital output resolved by the comparator. Used in this manner, latched comparators are used as components of analog-to-digital converters (ADCs) in a variety of applications.
In order to adapt a latched comparator such that it can evaluate low voltage inputs and generate a relatively large output signal, a latched comparator may be combined with an amplifier. Preceding the latched comparator, the preamplifier provides gain. The combined amplifier based comparator may be used in in memory devices for sensing the voltage of an individual memory cell and providing a digitized logical output representing the state of the memory cell.
An amplifier based comparator consists of pairs of complimentary transistors. Manufacturing variances in these transistors results in an input offset voltage that affects the operation of the amplifier based comparator. Such variances in the preamplifier may be amplified, such that the offset of the preamplifier dominates any offset present in the comparator. The input offset voltage reflects that additional input voltage that must be applied due to these manufacturing variances in order to trigger a change in state in the output of the sense amplifier based comparator. This offset changes the analog value at which the output of a comparator changes from zero to one, thus degrading the accuracy of the sense amplifier based comparator. The greater the offset, the greater the impact on the range of the sense amplifier based comparator. This offset may be accounted for using conventional techniques that cancel the offset.
Conventional input offset cancellation methods may effectively reduce offset, but do so at the expense of speed. In additional to reducing the operating speed of the circuit, conventional input offset cancellation techniques may increase the die area required by the circuit, increase the power requirements of the circuit and/or reduce the range of the inputs to the sense amplifier based comparator.